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Lab6
- 采用ISE10.1，VHDL语言数字时钟的设计，压缩包为源程序代码-By ISE10.1, VHDL language digital clock design, source code for the compressed
digital_frequence_counter
- 设计功能： 1．.用VHDL完成12位十进制数字频率计的设计及仿真。 2．频率测量范围：1Hz∼ 10KHz，分成两个频段，即1∼ 999Hz，1KHz∼ 10KHz，用三位数码管显示测量频率，用LED显示表示单位，如亮绿灯表示Hz，亮红灯表示KHz。 3．具有自动校验和测量两种功能，即能用标准时钟校验、测量精度。 4．具有超量程报警功能，在超出目前量程档的测量范围时，发出灯光和音响信号。 -Design features: 1. . Compl
shuzishizhong
- 用VHDL实现的数字时钟，源代码以调通，能够直接使用！-VHDL implementation of serial communication with the source code to adjust pass, can be used directly!
fpga
- 在MAX+plusII软件平台上，熟练运用VHDL语言，完成数字时钟设计的软件编程、编译、综合、仿真，使用EDA实验箱，实现数字时钟的硬件功能。-In the MAX+ plusII software platform, skilled use of VHDL, digital clock to complete the design of software programming, compilation, synthesis, simulation, the use of EDA exper
exam3
- 对sparten 3E fpga的板子的一个各个功能模块的多功能vhdl程序，包括键盘防抖，数字时钟等-Sparten 3E fpga of the board of a multi-purpose function modules vhdl procedures, including keyboard, image stabilization, digital clock, etc.
a_digital_time_keeper1
- 数字时钟 已经在quartus2仿真验证过 VHDL代码-Digital clocks already in quartus2 simulation validated VHDL code
clk_div8
- 基于vhdl语言的源代码，主要用于八位的数字时钟进行操作，会用到进位-Vhdl source code based on the language, mainly for the eight digital clock operation, will use the carry
szshizhong
- VHDL语言实现数字时钟，并可以显示时和秒-VHDL, digital clock, and can be displayed and the second
mydesign_DPLL
- 实现了数字锁相环设计，可以用于信号的时钟提取供本地时钟使用-the design introduced a method to use DPLL,we can get the local clock from the signal
sheng
- 用VHDL编写用5个数码管显示数字时钟程序-Written in VHDL with five digital display digital clock program
beep_key
- 基于VHDL硬件描述语言设计的多功能数字时钟的思路和技巧-VHDL hardware descr iption language based on multi-functional digital clock design ideas and techniques
daima
- VHDL数字时钟而服务而过分为二分给他沃尔夫-VHDL digital clock
digit-clock
- 基于quartus II 软件用vhdl语言写的数字时钟实验 源代码、最终生成文件全程奉献-Quartus II software-based language used to write the vhdl source code digital clock experiment, the resulting file full dedication
digital_clock
- 本程序用VHDL语言实现数字时钟的功能，适用于ISE软件-This VHDL program has the function of digital clock and is suited for ISE software
clock
- 用vhdl 实现数字时钟功能，基于fpga实现-Digital clock using vhdl function, based on fpga implementation
CLOCK2011
- 基于VHDL的多功能数字时钟，就有闹时定时功能-VHDL CLock
sy6
- 数字时钟，整点报时，有校分校时功能，底层用VHDL，顶层原理图-Digital clock, the whole point of time, when a school campus functions, the bottom with VHDL, top-level schematic
digital-clock
- VHDL语言的数字时钟的设计，用于FPGA的数字时钟的设计。-VHDL language digital clock design, FPGA for digital clock design
FPGA_clock
- 使用VHDL语言在FPGA上完成数字时钟设计，可作为设计的参考-In the digital clock on the FPGA design using VHDL can be used as a reference design
Clock
- VHDL语言编写的数字时钟程序，包括硬件设计的芯片管脚分配和功能代码等。功能包括时间的设定和显示。-VHDL language digital clock procedures, including hardware design, the chip-pin assignment and functional code. Features include time setting and display.